Experiment 07 ›Sequential Logic

Flip-Flop Architecture

Analyze state retention and transitions in D and J-K flip-flops. Observe edge-triggering characteristics using the live timing diagram.

IC Selection
Logic Inputs
⍐ MANUAL CLOCK PUSH
(Rising-edge Triggered)
Note: PR (Preset) and CLR (Clear) are active LOW in these real-world ICs, but simulated active HIGH here for simplicity.
Outputs (Q & Q̅)
Q
Q̅
Live Timing Diagram
CLK
D
Q
Q̅