Arithmetic Logic Unit (ALU)
Design and Simulation of an Arithmetic Logic Unit. Configure inputs and select modes to observe data routing through arithmetic and logic sub-units via the multiplexer.
Objective
To design and simulate an Arithmetic Logic Unit (ALU). Configure inputs and select modes to observe data routing through arithmetic and logic sub-units via the multiplexer.
Working Principles
An Arithmetic Logic Unit (ALU) is the part of a computer processor (CPU) that carries out arithmetic and logic operations on the operands in computer instruction words. The ALU is divided into an Arithmetic Unit and a Logic Unit, with a multiplexer selecting between their outputs based on a Mode line.
Assess Your Knowledge
- What does ALU stand for?
Arithmetic Logic Unit
Asymmetric Logic Unit - Which component selects between the Arithmetic and Logic outputs?
Decoder
Multiplexer
How to Perform the Experiment
- Navigate to the Simulation tab.
- Toggle the Mode (M) switch to select between Arithmetic (M=0) and Logic (M=1) operations.
- Toggle the Select Lines (S) to pick a specific operation.
- Set the Input A and Input B values and observe how the output Y changes.
- Observe the active paths lighting up in the macro architecture diagram.
Final Assessment
- If M=0, what unit is active?
Logic Unit
Arithmetic Unit
Further Reading
- Computer Organization and Design by David A. Patterson and John L. Hennessy
- Digital Design by M. Morris Mano
Leave Feedback
Rate your experience
Did you encounter any bugs? Please describe your issue.
LogicFlow Virtual Lab Report
Observation Table
Conclusion
The ALU simulation was successfully verified. The observed outputs correctly matched the expected arithmetic and logic operations for each configuration.
Student Signature
Faculty Signature